72 pin SIMM

SIMM=Single Inline Memory Module

72 PIN SIMM (at the computer)

72 PIN SIMM at the computer.

Pin	Non-Parity	Parity	Description
1	VSS	VSS	Ground
2	DQ0	DQ0	Data 0
3	DQ16	DQ16	Data 16
4	DQ1	DQ1	Data 1
5	DQ17	DQ17	Data 17
6	DQ2	DQ2	Data 2
7	DQ18	DQ18	Data 18
8	DQ3	DQ3	Data 3
9	DQ19	DQ19	Data 19
10	VCC	VCC	+5 VDC
11	n/c	n/c	Not connected
12	A0	A0	Address 0
13	A1	A1	Address 1
14	A2	A2	Address 2
15	A3	A3	Address 3
16	A4	A4	Address 4
17	A5	A5	Address 5
18	A6	A6	Address 6
19	A10	A10	Address 10
20	DQ4	DQ4	Data 4
21	DQ20	DQ20	Data 20
22	DQ5	DQ5	Data 5
23	DQ21	DQ21	Data 21
24	DQ6	DQ6	Data 6
25	DQ22	DQ22	Data 22
26	DQ7	DQ7	Data 7
27	DQ23	DQ23	Data 23
28	A7	A7	Address 7
29	A11	A11	Address 11
30	VCC	VCC	+5 VDC
31	A8	A8	Address 8
32	A9	A9	Address 9
33	/RAS3	/RAS3	Row Address Strobe 3
34	/RAS2	/RAS2	Row Address Strobe 2
35	n/c	PQ3	Parity bit 3 (for the 3rd byte, bits 16-23)
36	n/c	PQ1	Parity bit 1 (for the 1st byte, bits 0-7)
37	n/c	PQ2	Parity bit 2 (for the 2nd byte, bits 8-15)
38	n/c	PQ4	Parity bit 4 (for the 4th byte, bits 24-31)
39	VSS	VSS	Ground
40	/CAS0	/CAS0	Column Address Strobe 0
41	/CAS2	/CAS2	Column Address Strobe 2
42	/CAS3	/CAS3	Column Address Strobe 3
43	/CAS1	/CAS1	Column Address Strobe 1
44	/RAS0	/RAS0	Row Address Strobe 0
45	/RAS1	/RAS1	Row Address Strobe 1
46	n/c	n/c	Not connected
47	/WE	/WE	Read/Write
48	n/c	n/c	Not connected
49	DQ8	DQ8	Data 8
50	DQ24	DQ24	Data 24
51	DQ9	DQ9	Data 9
52	DQ25	DQ25	Data 25
53	DQ10	DQ10	Data 10
54	DQ26	DQ26	Data 26
55	DQ11	DQ11	Data 11
56	DQ27	DQ27	Data 27
57	DQ12	DQ12	Data 12
58	DQ28	DQ28	Data 28
59	VCC	VCC	+5 VDC
60	DQ29	DQ29	Data 29
61	DQ13	DQ13	Data 13
62	DQ30	DQ30	Data 30
63	DQ14	DQ14	Data 14
64	DQ31	DQ31	Data 31
65	DQ16	DQ16	Data 16
66	n/c	n/c	Not connected
67	PD1	PD1	Presence Detect 1
68	PD2	PD2	Presence Detect 2
69	PD3	PD3	Presence Detect 3
70	PD4	PD4	Presence Detect 4
71	n/c	n/c	Not connected
72	VSS	VSS	Ground

Size:

Notes: A9 is a N/C on 256k and 512k modules.
A10 is a N/C on 256k, 512k, 1M and 4M modules.
RAS1/RAS3 are N/C on 256k, 1M and 4M modules.